Method and apparatus for improving supply noise rejection

ABSTRACT

An electrostatic discharge (ESD) circuit operable to protect an internal circuit from ESD events and protect the internal circuit from high-side supply noise.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority to commonly assigned U.S.Provisional Patent Application No. 60/470,625, filed on May 15, 2003,which is incorporated herein by reference in its entirety.

BACKGROUND

Electrostatic discharge (ESD) can damage integrated circuits (ICs). ESDis caused when a source of electrostatic potential (e.g., a human bodywith a static buildup of charge carriers) comes into contact with acircuit input. The electrostatic voltage may damage sensitive ICs if theelectrostatic voltage discharges through circuit elements. In order toprevent ESD damage to functional circuits on the IC, ESD protectivecircuits may be incorporated on the input/output (I/O) pads of the IC.The role of an ESD protection circuit is to ensure, that in case of anESD event, the electrostatic potential is shunted (or diverted) toground—i.e., the electrostatic potential can be discharged through theESD protective circuits, protecting the IC's functional circuits.

FIG. 1 illustrates a conventional ESD protection scheme for an IC 100including an I/O pad 102 and an internal circuit 104. The conventionalESD protection scheme includes ESD protection circuits 106, 108, and anESD clamp 110. ESD protection circuits 106, 108 are typically formed bydiodes (represented by D1 and D2 in FIG. 1). ESD protection circuit 106couples I/O pad 102 to a high-side supply VDD 112, and ESD protectioncircuit 108 couples I/O pad 102 to a low-side supply VSS 114. ESD clamp110 couples VDD 112 to VSS 114, and provides a discharge path betweenVDD 112 and VSS 114 during an ESD event.

There are four types of ESD events that can occur at I/O pad 102 withrespect to VDD 112 and VSS 114. The four types of ESD events are:

(1) I/O pad 102 to VDD 112, positive discharge pulse: An I/O pad 102 toVDD 112 positive discharge pulse occurs when a positive ESD exertsstress on I/O pad 102 with VDD 112 relatively grounded. VSS 114 floatsduring an I/O pad 102 to VDD 112 positive discharge pulse. As discussedabove, the role of an ESD protection circuit is to shunt ESD away froman IC's functional circuits. The I/O pad 102 to VDD 112 positive ESD isshunted away from internal circuit 104 as follows: ESD protectioncircuit 106 shunts ESD current (associated with the positive dischargepulse) from I/O pad 102 to VDD 112.

(2) I/O pad 102 to VDD 112, negative discharge pulse: An I/O pad 102 toVDD 112 negative discharge pulse occurs when a negative ESD exertsstress on I/O pad 102 with VDD 112 relatively grounded. VSS 114 floatsduring an I/O pad 102 to VDD 112 negative discharge pulse. The I/O pad102 to VDD 112 negative ESD is shunted away from internal circuit 104 asfollows: ESD clamp 110 shunts ESD current (associated with the negativedischarge pulse) from VDD 112 to VSS 114. ESD protection circuit 108shunts the ESD current from VSS 114 to I/O pad 102.

(3) I/O pad 102 to VSS 114, positive discharge pulse: An I/O pad 102 toVSS 114 positive discharge pulse occurs when a positive ESD exertsstress on I/O pad 102 with VSS 114 relatively grounded. VDD 112 floatsduring an I/O pad 102 to VSS 114 positive discharge pulse. The I/O pad102 to VSS 114 positive ESD is shunted away from internal circuit 104 asfollows: ESD protection circuit 106 shunts ESD current (associated withthe positive discharge pulse) from I/O pad 102 to VDD 112. ESD clamp 110shunts ESD current from VDD 112 to VSS 114.

(4) I/O pad 102 to VSS 114, negative discharge pulse: An I/O pad 102 toVSS 114 negative pulse occurs when a negative ESD exerts stress on I/Opad 102 with VSS 114 relatively grounded. VDD 112 floats during an I/Opad 102 to VSS 114 negative discharge pulse. The I/O pad 102 to VSS 114negative ESD is shunted away from internal circuit 104 as follows: ESDprotection circuit 108 shunts ESD current (associated with the negativedischarge pulse) from VSS 114 to I/O pad 102.

The conventional ESD protection scheme described above can generallyshunt potentially damaging electrostatic potential away from sensitivecircuitry (e.g., internal circuit 104). One limitation of theconventional ESD protection scheme is a large parasitic capacitance thatis typically associated with each of ESD protection circuits 106, 108.Such a large parasitic capacitance can couple noise appearing on VDD112—i.e., high-side supply noise—through ESD protection circuit 106 tointernal circuit 104, and adversely affect the performance andreliability of internal circuit 104.

SUMMARY

In general, in one aspect, this specification describes an electrostaticdischarge (ESD) protection circuit for discharging ESD events. The ESDprotection circuit includes an ESD protection circuit having a first andsecond terminal. The first terminal is coupled to an input/output (I/O)pad, and the second terminal coupled to a low-side supply (VSS). The ESDprotection circuit is operable to shunt ESD current during positive andnegative ESD events.

Particular implementations may include one or more of the followingfeatures. The ESD protection circuit can include circuit elementsselected from the group consisting of polymer devices, metal oxidesilicon (MOS) devices, and diodes. The ESD protection circuit caninclude two diodes that are in parallel and in opposite directions. TheESD protection circuit can not be directly coupled to a high-side supply(VDD). The ESD protection circuit can further include an ESD clamp toprovide a discharge path between the high-side supply (VDD) and thelow-side supply (VSS) during an ESD event. The positive and negative ESDevents can include an I/O pad to high-side supply (VDD) positivedischarge pulse, an I/O pad to high-side supply (VDD) negative dischargepulse, an I/O pad to low-side supply (VSS) positive discharge pulse, andan I/O pad to low-side supply (VSS) negative discharge pulse. Thelow-side supply (VSS) can float during the I/O pad to high-side supply(VDD) positive discharge pulse and the I/O pad to high-side supply (VDD)negative discharge pulse. The high-side supply (VDD) can float duringthe I/O pad to low-side supply (VSS) positive discharge pulse and theI/O pad to low-side supply (VSS) negative discharge pulse.

In general, in another aspect, this specification describes a method fordischarging electrostatic discharge (ESD). The method includes receivinga positive or negative discharge pulse on an I/O pad, and shunting ESDcurrent associated with the positive or negative discharge pulse fromthe I/O pad to a low-side supply (VSS) prior to shunting the ESD currentto a high-side supply (VDD) for all the received positive and negativedischarge pulses.

Particular implementations may include one or more of the followingfeatures. The positive discharge pulse can be an ESD event selected fromthe group consisting of an I/O pad to high-side supply (VDD) positivedischarge pulse and an I/O pad to low-side supply (VSS) positivedischarge pulse. If the positive discharge pulse is an I/O pad tohigh-side supply (VDD) positive discharge pulse, shunting ESD currentcan include shunting ESD current associated with the I/O pad tohigh-side supply (VDD) positive discharge pulse from the I/O pad to thelow-side supply (VSS), then shunting the ESD current from the low-sidesupply (VSS) to the high-side supply (VDD). If the positive dischargepulse is an I/O pad to low-side supply (VSS) positive discharge pulse,shunting ESD current can include shunting ESD current associated withthe I/O pad to low-side supply (VSS) positive discharge pulse from theI/O pad to the low-side supply (VSS).

The negative discharge pulse can be an ESD event selected from the groupconsisting of an I/O pad to high-side supply (VDD) negative dischargepulse and an I/O pad to low-side supply (VSS) negative discharge pulse.If the negative discharge pulse is an I/O pad to high-side supply (VDD)negative discharge pulse, shunting ESD current can include shunting ESDcurrent associated with the I/O pad to high-side supply (VDD) Negativedischarge pulse from the high-side supply VDD to the low-side supply(VDD), then shunting the ESD current from the low-side supply (VSS) tothe I/O pad. If the negative discharge pulse is an I/O pad to low-sidesupply (VSS) negative discharge pulse, shunting ESD current can includeshunting ESD current associated with the I/O pad to low-side supply(VSS) negative discharge pulse from the low-side supply VSS to the I/Opad.

In general, in another aspect, this specification describes a low noiseamplifier (LNA). The LNA includes an RF input and an electrostaticdischarge (ESD) protection circuit. The ESD protection circuit includesa first terminal coupled to an input/output (I/O) pad, and a secondterminal coupled to a low-side supply (VSS). The ESD protection circuitis operable to shunt ESD current during positive and negative ESD eventsaway from the RF input and through the low-side supply.

Particular implementations may include one or more of the followingfeatures. The low noise amplifier can be compliant with an IEEE standardselected from the group consisting of 802.11, 802.11a, 802.11b, 802.11e,802.11g, 802.11h, and 802.11i, and 802.14.

An ESD protection scheme is provided that protects an internal circuitfrom high-side supply noise. The ESD protection scheme does not includean ESD protection circuit that couples the high-side supply to theinternal circuit. Thus, there is not a direct path for any high-sidesupply noise to travel from the high-side supply to the internalcircuit. The ESD protection scheme, therefore, provides a betterrejection of high-side supply noise.

The details of one or more implementations are set forth in theaccompanying drawings and the description below. Other features andadvantages will be apparent from the description and drawings, and fromthe claims.

DESCRIPTION OF DRAWINGS

FIG. 1 illustrates a conventional ESD protection scheme for an IC.

FIG. 2 illustrates an ESD protection scheme for an IC.

FIG. 3 illustrates an ESD protection circuit.

FIG. 4 is a flowchart of a process for discharging ESD.

FIG. 5 is schematic diagram of a low noise amplifier (LNA).

FIG. 6 illustrates an ESD protection circuit for a low noise amplifier.

FIG. 7 illustrates an ESD protection scheme for an IC.

FIG. 8 illustrates an ESD protection scheme for ICs within a singlesupply group.

FIG. 9 illustrates an ESD protection scheme for ICs within a differentsupply group.

Like reference symbols in the various drawings indicate like elements.

DETAILED DESCRIPTION

FIG. 2 illustrates an ESD protection scheme for an IC 200 including anI/O pad 202 and an internal circuit 204 that are both immune from highsupply noise. The ESD protection scheme includes an ESD protectioncircuit 206 and an ESD clamp 208, to protect internal circuit 204 fromESD events. ESD clamp 208 couples a high-side supply (VDD 210) to alow-side supply (VSS 212) and provides a discharge path between VDD 210and VSS 212 during an ESD event. ESD protection circuit 206 couples I/Opad 202 to VSS 212. As shown in FIG. 2, IC 200 does not include an ESDprotection circuit to couple I/O pad 202 to VDD 210. Thus, there is nota direct path for any high supply noise (i.e., noise from VDD 210) totravel from VDD 210 to internal circuit 204.

ESD protection circuit 206 can be formed by polymer devices and/or metaloxide silicon (MOS) devices (e.g., transistors). ESD protection circuitcan include diodes (e.g., regular diodes, Zener diodes, TVS (transientvoltage suppression) diodes, MOVs (metal oxide varistors), siliconcontrolled rectifiers (SCRs), and so on), and be operable to shuntpositive and negative ESD current away from internal circuit 204. Morespecifically, ESD protection circuit 206 provides the followingfunctions upon occurrence of ESD events, as shown in FIG. 2.

(1) I/O pad 202 to VDD 210, positive discharge pulse: An I/O pad 202 toVDD 210 positive discharge pulse occurs when a positive ESD exertsstress on I/O pad 202 with VDD 210 relatively grounded. VSS 212 floatsduring an I/O pad 202 to VDD 210 positive discharge pulse. The role ofESD protection circuit 206 is to shunt ESD away from internal circuit204. The I/O pad 202 to VDD 112 positive discharge pulse is shunted awayfrom internal circuit 204 as follows: ESD protection circuit 206 shuntsthe ESD current (associated with the positive discharge pulse) from I/Opad 202 to VSS 212. ESD clamp 208 shunts the ESD current from VSS 212 toVDD 210.

(2) I/O pad 202 to VDD 210, negative discharge pulse: An I/O pad 202 toVDD 210 negative discharge pulse occurs when a negative ESD exertsstress on I/O pad 202 with VDD 210 relatively grounded. VSS 212 floatsduring an I/O pad 202 to VDD 210 negative discharge pulse. The I/O pad202 to VDD 112 negative discharge pulse is shunted away from internalcircuit 204 as follows: ESD clamp 208 shunts the ESD current (associatedwith the negative discharge pulse) from VDD 210 to VSS 212. ESDprotection circuit 206 shunts the ESD current from VSS 212 to I/O pad202.

(3) I/O pad 202 to VSS 212, positive discharge pulse: An I/O pad 202 toVSS 212 positive discharge pulse occurs when a positive ESD exertsstress on I/O pad 202 with VSS 212 relatively grounded. VDD 210 floatsduring an I/O pad 202 to VSS 212 positive discharge pulse. The I/O pad202 to VSS 212 positive discharge pulse is shunted away from internalcircuit 204 as follows: ESD protection circuit 206 shunts the ESDcurrent (associated with the positive discharge pulse) from I/O pad 202to VSS 212.

(4) I/O pad 202 to VSS 212, negative discharge pulse: An I/O pad 202 toVSS 212 negative discharge pulse occurs when a negative ESD exertsstress on I/O pad 202 with VSS 212 relatively grounded. VDD 210 floatsduring an I/O pad 202 to VSS 212 negative discharge pulse. The I/O pad202 to VSS 212 negative discharge pulse is shunted away from internalcircuit 204 as follows: ESD protection circuit 206 shunts the ESDcurrent (associated with the negative discharge pulse) from VSS 212 toI/O pad 202.

FIG. 3 illustrates an implementation of ESD protection circuit 206formed by a first diode 300 and a second diode 302. As shown in FIG. 3,first diode 300 and second diode 302 are coupled in parallel, and inopposite directions, between I/O pad 202 and VSS 212. That is, firstdiode 300 has an anode and a cathode coupled to VSS 212 and I/O pad 202,respectively, and second diode 302 has an anode and a cathode coupled toI/O pad 202 and VSS 212, respectively. ESD protection circuit 206,formed by first diode 300 and second diode 302, protects internalcircuit 204 from ESD events.

(1) I/O pad 202 to VDD 210, positive discharge pulse: As discussedabove, an I/O pad 202 to VDD 210 positive discharge pulse occurs when apositive ESD exerts stress on I/O pad 202 with VDD 210 relativelygrounded. VSS 212 floats during an I/O pad 202 to VDD 210 positivedischarge pulse. Second diode 302 shunts the ESD current (associatedwith the positive discharge pulse) from I/O pad 202 to VSS 212. ESDclamp 208 shunts the ESD current from VSS 212 to VDD 210.

(2) I/O pad 202 to VDD 210, negative discharge pulse: An I/O pad 202 toVDD 210 negative discharge pulse occurs when a negative ESD exertsstress on I/O pad 202 with VDD 210 relatively grounded. VSS 212 floatsduring an I/O pad 202 to VDD 210 negative discharge pulse. The I/O pad202 to VDD 112 negative discharge pulse is shunted away from internalcircuit 204 as follows: ESD clamp 208 shunts the ESD current (associatedwith the negative discharge pulse) from VDD 210 to VSS 212. First diode300 shunts the ESD current from VSS 212 to I/O pad 202.

(3) I/O pad 202 to VSS 212, positive discharge pulse: An I/O pad 202 toVSS 212 positive discharge pulse occurs when a positive ESD exertsstress on I/O pad 202 with VSS 212 relatively grounded. (VDD 210 floatsduring an I/O pad 202 to VSS 212 positive discharge pulse. The I/O pad202 to VSS 212 positive discharge pulse is shunted away from internalcircuit 204 as follows: Second diode 302 shunts the ESD current(associated with the positive discharge pulse) from I/O pad 202 to VSS212.

(4) I/O pad 202 to VSS 212, negative discharge pulse: An I/O pad 202 toVSS 212 negative discharge pulse occurs when a negative ESD exertsstress on I/O pad 202 with VSS 212 relatively grounded. VDD 210 floatsduring an I/O pad 202 to VSS 212 negative discharge pulse. The I/O pad202 to VSS 212 negative discharge pulse is shunted away from internalcircuit 204 as follows: First diode 300 shunts the ESD current(associated with the negative discharge pulse) from VSS 212 to I/O pad202.

FIG. 4 shows one implementation of a process 400 for providing an ESDprotection scheme for an internal circuit. An ESD event occurs on an I/Opad (step 402). If the ESD event is an I/O pad to VDD, positivedischarge pulse, ESD current is first directly shunted from the I/O padto VSS through an ESD protection circuit (step 404). The ESD current isthen directly shunted from VSS to VDD through an ESD clamp (step 406).If the ESD event is an I/O pad to VDD, negative discharge pulse, ESDcurrent is first directly shunted from VDD to VSS through an ESD clamp(step 408). The ESD current is then directly shunted from VSS to the I/Opad through an ESD protection circuit (step 410). If the ESD event is anI/O pad to VSS, positive discharge pulse, ESD current is directlyshunted from the I/O pad to VSS through an ESD protection circuit (step412). If the ESD event is an I/O pad to VSS, negative discharge pulse,ESD current is directly shunted from VSS to the I/O pad through an ESDprotection circuit (step 414).

The ESD protection scheme illustrated in FIGS. 2 and 3 can be used toprotect a wide range of circuits, e.g., a low noise amplifier (LNA). ALNA is a critical building block of an RF transceiver which is sensitiveto high-side supply noise. FIG. 5 shows an example of a conventionalCMOS LNA 500. CMOS LNA 500 includes an RF input 502. CMOS LNA 500 can beIEEE compliant with the following IEEE standards—802.11, 802.11a,802.11b, 802.11e, 802.11g, 802.11h, 802.11i, and 802.14.

Referring to FIG. 6, ESD protection circuit 206 is particularly suitableto protect LNA circuits due to LNA circuits having relatively low inputvoltage swings—(e.g., lower than 0.6V-0.7V). That is, the input voltageswings are low enough such that neither of diodes 300, 302 are activatedby the input voltage swings.

Other Implementations

An internal circuit can have an input that is referenced to a high-sidesupply VDD instead of a low-side supply VSS—e.g., the internal circuitcan have a p-type input device such as a PMOS transistor or a PNPbipolar transistor. In this case, the ESD protection scheme can bemodified as shown in FIG. 7, in which case ESD protection circuit 206couples an internal circuit 700 (having a p-type input device) tohigh-side supply VDD instead of low-side supply VSS.

FIG. 8 shows an ESD protection scheme including ESD protection circuits206A, 206B to protect internal circuits 802, 804 (within a singlehigh-side supply group—i.e., VDD 810) against pin-to-pin zapping betweenI/O pins 806, 808. For example, an I/O pad 806 to I/O pad 808 positivedischarge pulse can occur when a positive ESD exerts stress on I/O pad806 with I/O pad 808 relatively grounded. In such a case, the role ofESD protection circuits 206A, 206B is to shunt the positive ESD awayfrom internal circuits 802, 804. The positive I/O pad 806 to I/O pad 808positive discharge pulse is shunted away from internal circuits 802, 804as follows: ESD protection circuit 206A shunts the ESD current from I/Opad 806 to VSS 812. ESD protection circuit 206B shunts the ESD currentfrom VSS 812 to I/O pad 808. A positive discharge pulse from I/O pad 808to I/O pad 806 can similarly be discharged.

FIG. 9 shows an ESD protection scheme including ESD protection circuits206A, 206B, and ESD clamps 208A, 208B to protect internal circuits 902,904 (within different high-side supply groups—i.e., VDD 910, 912)against pin-to-pin zapping between I/O pins 906, 908, and PIN to supplyzapping. Pin-to-pin zapping between I/O pins 906, 908 can be dischargedas discussed above with respect to the ESD protection scheme of FIG. 8.

A number of implementations of the invention have been described.Nevertheless, it will be understood that various modifications may bemade. For example, the ESD protection scheme can be used to protectcircuits having a low input voltage swing (e.g., lower than 0.6V-0.7V),and a low bias voltage. Also, FIGS. 8 and 9 can have internal circuitsthat have inputs referenced to a high-side supply VDD instead of alow-side supply VSS. Accordingly, other implementations are within thescope of the following claims.

1. A low noise amplifier, comprising: a radio frequency input; an electrostatic discharge protection circuit including: a pair of diodes each having a first and a second terminal; a first diode of the pair having a first terminal coupled to the radio frequency input and a second terminal directly coupled to a low voltage supply; and a second diode of the pair having a second terminal coupled to the radio frequency input and a first terminal directly coupled to the low voltage supply; and an electrostatic discharge clamp directly coupled between a high voltage supply and the low voltage supply so as to provide a discharge path between the high voltage supply and the low voltage supply during an electrostatic discharge event, wherein the electrostatic discharge protection circuit is operable to float the low voltage supply and to shunt: the radio frequency input to high voltage supply positive discharge pulse using the second diode and the electrostatic discharge clamp, and the radio frequency input to high voltage supply negative discharge pulse using the first diode and the electrostatic discharge clamp.
 2. The low noise amplifier of claim 1, wherein the first and second diodes are formed by one of polymer devices and metal oxide silicon devices.
 3. The low noise amplifier of claim 1, further comprising an additional circuit of the low noise amplifier associated with the radio frequency input wherein: if the additional circuit is referenced to the low voltage supply, then the electrostatic discharge protection circuit is not directly coupled to the high voltage supply; and if the additional circuit is referenced to the high voltage supply, then the electrostatic discharge protection circuit is not directly coupled to the low voltage supply.
 4. The low noise amplifier of claim 1, wherein the low noise amplifier is compliant with an IEEE standard selected from the group consisting of 802.11, 802.11a, 802.11b, 802.11e, 802.11g, 802.11h, and 802.11i, and 802.14.
 5. A low noise amplifier, comprising: a radio frequency input; an electrostatic discharge protection circuit including: a pair of diodes each having a first and a second terminal; a first diode of the pair having a first terminal coupled to the radio frequency input and a second terminal directly coupled to a low voltage supply; and a second diode of the pair having a second terminal coupled to the radio frequency input and a first terminal directly coupled to the low voltage supply; and an electrostatic discharge clamp directly coupled between a high voltage supply and the low voltage supply so as to provide a discharge path between the high voltage supply and the low voltage supply during an electrostatic discharge event, wherein the electrostatic discharge protection circuit is operable to float the high voltage supply and to shunt: the radio frequency input to low voltage supply positive discharge pulse using the second diode, and the radio frequency input to low voltage supply negative discharge pulse using the first diode.
 6. The low noise amplifier of claim 5, wherein the first and second diodes are formed by one of polymer devices and metal oxide silicon devices.
 7. The low noise amplifier of claim 5, further comprising an additional circuit of the low noise amplifier associated with the radio frequency input wherein: if the additional circuit is referenced to the low voltage supply, then the electrostatic discharge protection circuit is not directly coupled to the high voltage supply; and if the additional circuit is referenced to the high voltage supply, then the electrostatic discharge protection circuit is not directly coupled to the low voltage supply.
 8. The low noise amplifier of claim 5, wherein the low noise amplifier is compliant with an IEEE standard selected from the group consisting of 802.11, 802.11a, 802.11b, 802.11e, 802.11g, 802.11h, and 802.11i, and 802.14.
 9. An electrostatic discharge protection circuit, comprising: a pair of diodes each having a first and a second terminal; a first diode of the pair having a first terminal coupled to an input/output pad and a second terminal directly coupled to a low voltage supply; and a second diode of the pair having a second terminal coupled to the input/output pad and a first terminal directly coupled to the low voltage supply; and an electrostatic discharge clamp directly coupled between a high voltage supply and the low voltage supply so as to provide a discharge path between the high voltage supply and the low voltage supply during an electrostatic discharge event, wherein the electrostatic discharge protection circuit is operable to float the low voltage supply and to shunt: the input/output pad to high voltage supply positive discharge pulse using the second diode and the electrostatic discharge clamp, and the input/output pad to high voltage supply negative discharge pulse using the first diode and the electrostatic discharge clamp.
 10. The circuit of claim 9, wherein the first and second diodes are formed by one of polymer devices and metal oxide silicon devices.
 11. The circuit of claim 9, wherein the input/output pad is associated with a separate circuit and: if the separate circuit is referenced to the low voltage supply, then the electrostatic discharge protection circuit is not directly coupled to the high voltage supply; and if the separate circuit is referenced to the high voltage supply, then the electrostatic discharge protection circuit is not directly coupled to the low voltage supply.
 12. An electrostatic discharge protection circuit, comprising: a pair of diodes each having a first and a second terminal; a first diode of the pair having a first terminal coupled to an input/output pad and a second terminal directly coupled to a low voltage supply; and a second diode of the pair having a second terminal coupled to the input/output pad and a first terminal directly coupled to the low voltage supply; and an electrostatic discharge clamp directly coupled between a high voltage supply and the low voltage supply so as to provide a discharge path between the high voltage supply and the low voltage supply during an electrostatic discharge event, wherein the electrostatic discharge protection circuit is operable to float the high voltage supply and to shunt: an input/output pad to low voltage supply positive discharge pulse using the second diode, and an input/output pad to low voltage supply negative discharge pulse using the first diode.
 13. The circuit of claim 12, wherein the first and second diodes are formed by one of polymer devices and metal oxide silicon devices.
 14. The circuit of claim 12, wherein the input/output pad is associated with a separate circuit and: if the separate circuit is referenced to the low voltage supply, then the electrostatic discharge protection circuit is not directly coupled to the high voltage supply; and if the separate circuit is referenced to the high voltage supply, then the electrostatic discharge protection circuit is not directly coupled to the low voltage supply.
 15. A method for discharging electrostatic discharge, comprising: providing a first direct discharge path between an input/output pad and a low voltage supply; providing a second direct discharge path between the input/output pad and the low voltage supply; providing a third discharge path between the low voltage supply and a high voltage supply during an electrostatic discharge event; and floating the low voltage supply while shunting an input/output pad to high voltage supply positive discharge pulse using the second direct discharge path and the third discharge path, and shunting an input/output pad to high voltage supply negative discharge pulse using the first direct discharge path and the direct discharge path.
 16. The method of claim 15, wherein the input/output pad is associated with a circuit and: if the circuit is referenced to the low voltage supply, then not providing a direct discharge path between the input/output pad and the high voltage supply; and if the circuit is referenced to the high voltage supply, then not providing a direct discharge path between the input/output pad and the low voltage supply.
 17. A method for discharging electrostatic discharge, comprising: providing a first direct discharge path between an input/output pad and a low voltage supply; providing a second direct discharge path between the input/output pad and the low voltage supply; providing a third discharge path between the low voltage supply and a high voltage supply during an electrostatic discharge event; and floating the high voltage supply while shunting an input/output pad to low voltage supply positive discharge pulse using the second direct discharge path, and shunting an input/output pad to low voltage supply negative discharge pulse using the first direct discharge path.
 18. The method of claim 17, wherein the input/output pad is associated with a circuit and: if the circuit is referenced to the low voltage supply, then not providing a direct discharge path between the input/output pad and the high voltage supply; and if the circuit is referenced to the high voltage supply, then not providing a direct discharge path between the input/output pad and the low voltage supply. 